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100 Commits

Author SHA1 Message Date
wfjm
dd7cdfeceb add w11a system for Arty with MIG 2019-01-04 09:19:00 +01:00
wfjm
cb7b906089 Add memory tester for Arty and MIG 
- sys_tst_sram_arty: add system and tb
- sramif_mig_arty: add SRAM to DDR via MIG adapter for arty
- cdc_pulse: add clock domain crossing for a slowly changing value
- cdc_vector_s0: add ENA port (now used in cdc_pulse)
- tst_mig/util.tcl: test_rwait: add optional lena argument
- viv_tools_build.tcl: downgrade SSN critical warnings to warnings
 2019-01-03 09:15:07 +01:00
wfjm
0e87dd8670 add sramif2migui: w11a SRAM to MIG UI interface core 2019-01-02 10:06:25 +01:00
wfjm
f50a85e646 add sys_tst_mig_arty system: a MIG tester 2019-01-01 22:41:44 +01:00
wfjm
14362b2a56 Add basic DDR memory support 
- arty board support
- viv_tools_build: export log and rpt generated in OOC synthesis runs
- s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper
- s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk
- cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input
- migui_core_gsim: highly simplified MIG UI simulation model
 2018-12-31 10:00:14 +01:00
wfjm
cf6c0ed8e0 cleanup not longer used directory 2018-12-30 10:59:24 +01:00
wfjm
b8dfa6d41e get ready for w11a_V0.753 release 
- rtl/sys_gen/*/*.vhd: drop superfluous genlib call
- rtl/sys_gen/*/*.vmfset: accomodate recent code changes
- tools/bin/tbrun: show correct 'found count' in summary message
- tools/dox/*.Doxyfile: push version to 0.753
- tools/src/librtools/Rtime.ipp: change list-init make some gcc happy
 2018-12-29 14:14:08 +01:00
wfjm
89732fe3e0 update xviv_msg_filter 
- add c type rules for 'count-only' filters
- add support for bitstream generation checking ([bit] section)
- update vmfsets
 2018-12-26 09:40:03 +01:00
wfjm
674762d6d8 consolidate clock generation in 7-Series designs 
- s7_cmt_1ce1ce: add clock generator block used in many 7-Series designs
- sys_gen/*/*: use s7_cmt_1ce1ce in 7-Series designs
- tbcore_rlink: wait 40 cycles after CONF_DONE
- serport_master_tb: add 100 ps RXSD,TXSD delay to allow clock jitter
 2018-12-21 09:06:16 +01:00
wfjm
233730885d comment&code cosmetics; minor changes 2018-12-08 09:25:25 +01:00
wfjm
5d34d1fad6 ensure that essential vivado warnings are not discarded 
- xviv_msg_filter: display INFO Common 17-14 'further message disabled'
- viv_tools_build.tcl: increase message limits (all 200, some 5000)
- sys_w11a_*.vmfset: correct for thus far missed entries
 2018-12-07 19:38:32 +01:00
wfjm
a3bf3519d9 remove ISE build support for 7Series designs 2018-12-01 13:07:59 +01:00
wfjm
e1abc27983 comment&code cosmetics; minor changes 2018-11-11 09:50:46 +01:00
wfjm
22bb8e011c reorganize dcm/mmcm/ppl sim models 
- sfs_gsim_core: new common simulation core
- {dcm,s6_cmt,s7_cmt}_sfs_gsim: use now sfs_gsim_core
- s7_cmt_sfs_tb: removed, use now sfs_gsim_core
- rtl/bplib/*/tb/tb_*: use now sfs_gsim_core
- tst_serloop/nexys*/tb/tb_tst_serloop*_n*: use now sfs_gsim_core
 2018-11-09 17:48:56 +01:00
wfjm
0913863793 comment&code cosmetics; minor changes 2018-11-03 10:30:00 +01:00
wfjm
90db21ac5e update vivado design vmfset files 2018-10-14 15:06:24 +02:00
wfjm
37b2d63281 finalize IDEC and PERFEXT wiring 
- ibdr_maxisys: add IDEC port, connect to EXTEVT of KW11P
- sys_w11a_*.vhd: use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
- kw11p and dmpcnt now fully setup
 2018-10-14 15:02:45 +02:00
wfjm
3eedd7f5c8 comment&code cosmetics; minor changes 2018-10-14 14:57:39 +02:00
wfjm
c7e606d9b0 use DM_STAT_EXP for signals exported by pdp11_sys70 
- pdp11_sys70: drop ITIMER,DM_STAT_DP, use DM_STAT_EXP, add PERFEXT port
- pdp11_sequencer: drop ITIMER port, use DM_STAT_SE.itimer
- sys_w11a_*.vhd: use DM_STAT_EXP
- some re-wiring, no functional change to CPU or IO system
 2018-10-13 15:18:59 +02:00
wfjm
f40108cb95 drop DM_STAT_SY, add DM_STAT_CA and cache monitoring 2018-10-07 08:50:11 +02:00
wfjm
1be14ad15f Integrate dmpcnt in all w11 designs and backend 
- pdp11_sequencer: add DM_STAT_SE.(cpbusy,idec)
- pdp11_sys70: only preliminary set of signals, cache signals kludged
 2018-09-30 09:35:30 +02:00
wfjm
f838fc3b4d add pdp11_dmpcnt: performance counters 2018-09-29 17:33:33 +02:00
wfjm
4df1d3e549 minor comment corrections/additions 2018-09-21 19:35:31 +02:00
wfjm
ff7b4fad97 integrate KW11-P in all w11 designs 2018-09-15 17:27:46 +02:00
wfjm
17ede0047a add ibd_kw11p: KW11-P prog clock 2018-09-15 15:23:47 +02:00
wfjm
40d48680e9 finalize w11a_V0.752 release 2018-08-26 13:54:48 +02:00
wfjm
088f57df2c prepare w11a_V0.752 release 2018-08-26 10:03:24 +02:00
wfjm
010c79c0fc add w11a port to Arty S7 (BRAM only, sim-tested only) 2018-08-25 07:59:59 +02:00
wfjm
b24fd9a3cb add Digilent Arty S7 board support 2018-08-25 07:58:05 +02:00
wfjm
ac16d6d27e *.vmfset: update rules to cover 2017.4-2018.2 2018-08-24 20:52:21 +02:00
wfjm
b6074a354f _ssim.vbom: fix incorrect aif target 2018-08-12 08:41:52 +02:00
wfjm
286a8cdaff add forgotten tb_c7_sram_memctl 2018-08-10 22:17:22 +02:00
wfjm
5493c0f4f2 minor docu updates, add INSTALL_quickstart 2018-08-04 15:07:12 +02:00
wfjm
15a8f0e4e4 get disclaimers in line with GPL V3 License.txt 2018-01-03 10:04:30 +01:00
wfjm
dfa2a91a18 get disclaimers in line with GPL V3 License.txt 2018-01-02 21:57:40 +01:00
wfjm
8c57be520f c7_sram_memctl: shorten ce and oe time 2017-07-02 14:22:20 +02:00
wfjm
62eb016ec2 add missing file; minor updates 2017-07-01 13:42:40 +02:00
wfjm
05c7d937c7 Add Digilent Cmod A7 (35 die size) support 
- general board support
- c7_sram_memctl: SRAM memory controller (incl tb)
- is61wv5128bll: simple memory model (incl tb)
- sn_humanio_emu_rbus: human IO emulator
- 92-retro-usb-persistent.rules: add more board rules
- associated changes
  - sn_humanio_rbus: add stat_rbf_emu (=0); single cycle btn pulses
  - rgbdrv_analog(_rbus): add ACTLOW generic to invert output polarity
  - ti_rri: adopt Digilent autodetect for CmodA7
- add systems
  - tst_rlink: rlink tested
  - tst_sram: SRAM tester
  - w11a: w11a system with 672 kB memory (512 SRAM + 160 BRAM)
 2017-06-28 22:29:09 +02:00
wfjm
4aa1db49c7 Cleanups; 17bit support for tst_sram 
- s3_sram_memctl: drop superfluous idata_cei=1 in s_write2
- arty_bram/tb/tbrun.yml: retire mem70 - now in tbcpu
- tst_sram.vhd: allow AWIDTH=17; sstat_rbf_awidth instead of _wide
- tcl/tst_sram/*.tcl: 17bit support; use sstat(awidth); add isnarrow
- rtl/vlib/rutil.vhd: added package, with imin helper function
 2017-06-25 20:20:48 +02:00
wfjm
691b95c786 code cosmetics 2017-06-25 15:45:14 +02:00
wfjm
97f1539292 add test_w11a_mem70.tcl; retire old tests tb_w11a_mem70*.dat 2017-06-25 15:43:19 +02:00
wfjm
c2c192abe9 comment changes 2017-06-11 20:39:43 +02:00
wfjm
211e1f3ff3 get vivado 2017.1 ready 
- xviv_msg_filter: add version-range tag support
- *.vmfset:
  - drop the nonsense 'Synth 8-6014' messages
  - adopt to different path used by 'Synth 8-3332' messages
 2017-06-10 11:36:32 +02:00
wfjm
27de682629 minor docu changes 2017-06-05 23:09:02 +02:00
wfjm
5d3504b01a documentation updates 2017-06-04 09:08:37 +02:00
wfjm
a9425599e7 Miscellaneous fixes and changes 
- ibdr_deuna: add logic to handle 'PDMD issued while busy'
- Rw11CntlDEUNA: adopt trace and statistics
- hook_ibmon_xua.tcl: use .imf,.ime
 2017-05-28 13:33:39 +02:00
Walter F.J. Mueller
9e309c81b9 Miscellaneous fixes and changes 
- Makefile: add all_tcl to all; use njobihtm
- rlink_core: BUGFIX: correct re-transmit after nak aborts
- tb_rlink_stim.dat: start section B (error aborts) and C (retransmit)
- ticonv_rri: use 'rlc rawwblk' instead of 'rlc rawio -wblk'
- rbmoni/test_regs.tcl: add data/addr logic tests
 2017-05-07 18:57:45 +02:00
Walter F.J. Mueller
7977206a8b code and comment cosmetics 2017-05-07 18:54:16 +02:00
Walter F.J. Mueller
3d3035eb96 correct spelling 2017-04-30 15:33:23 +02:00
Walter F.J. Mueller
eb53dc6bfd use SWI(7:6) to allow fx2 debug via LEDs 2017-04-30 15:14:56 +02:00