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2026-03-01 17:26:11 +00:00
671953941f
Add FSR to Vex, use it for unaligned blits
2021-11-01 14:34:34 +01:00
97f688dd7d
Merge branch 'main' of github.com:rdolbeau/SBusFPGA into main
2021-10-31 19:59:07 +01:00
2cda6c49d6
minor changes
2021-10-31 19:58:19 +01:00
c20d1f321f
smaller vex
2021-10-31 19:57:39 +01:00
afdfe4a686
support more Po2 FB sizes
2021-10-30 12:51:02 +02:00
6f04a9bd73
more configuratble blit rom
2021-10-30 11:53:09 +02:00
417095d2c0
extrac cycle to meet timings at 1920x1080@60 when using HW cursor
2021-10-30 11:52:58 +02:00
f57a22e434
add a (working this time) Dcache to Vex
2021-10-30 11:52:01 +02:00
c2da8f5633
more improvements
2021-10-30 11:41:05 +02:00
1344a2e7e7
Font for the on-screen debug display
2021-10-30 10:04:12 +02:00
a85542d029
CG6 accel emulation (still slow)
2021-10-30 10:03:11 +02:00
f5a1067806
fix broken timeout, some (disabled, for testing) stat stuff
2021-10-30 10:02:33 +02:00
06bff62901
move the wishbone CDC locally ; speedgrade from part
2021-10-30 10:01:26 +02:00
dea62d3d73
trying to improve the timing in the vga_clk domain
2021-10-24 20:02:59 +02:00
fa0387fe96
trying to improve the cg accel stuff
2021-10-24 20:02:34 +02:00
ee1e8d3450
Dcache-less Vex
2021-10-24 20:02:02 +02:00
5b8124b939
proto CG6
2021-10-15 22:38:27 +02:00
d552b1cd52
Merge branch 'main' of github.com:rdolbeau/SBusFPGA into main
2021-10-11 08:06:10 +02:00
8642dd8c40
Merge branch 'main' of github.com:rdolbeau/SBusFPGA into main
2021-10-11 08:05:26 +02:00
27a310fadf
one more word of warning
2021-10-11 08:05:15 +02:00
6c6cb87395
WB FSM was broken (cmap to be tested still)
2021-10-10 19:23:39 +02:00
3e95f078f5
fix irq priority handling in ohci-sbus device
2021-10-09 17:51:33 +02:00
232b7795cd
Merge branch 'main' of github.com:rdolbeau/SBusFPGA into main
2021-10-09 11:26:32 +02:00
bd992ad421
add VGA222 Pmod
2021-10-09 11:26:13 +02:00
e31ea588f1
don't need the extra 256 KiB
2021-10-09 11:19:47 +02:00
04612ea864
add a known limitation
2021-10-09 11:11:02 +02:00
f27c8d86f6
README in Pictures
2021-10-09 10:44:40 +02:00
018f271c67
pictures of V1.2
2021-10-09 10:40:38 +02:00
3afb728485
update README to V1.2
2021-10-09 10:39:51 +02:00
d417ba7206
Merge branch 'v1_2' into main
2021-10-09 10:26:03 +02:00
1c690cbd90
Merge branch 'main' of github.com:rdolbeau/SBusFPGA into main
2021-10-09 10:25:47 +02:00
0b3cd1bfb5
Merge branch 'main' of github.com:rdolbeau/SBusFPGA into main
2021-10-09 08:27:34 +02:00
93b69a4afb
Merge branch 'v1_2' of github.com:rdolbeau/SBusFPGA into v1_2
2021-10-09 08:09:24 +02:00
11cfd3ba40
CG3 is usable as console and with X11, despite the ugly colors
2021-10-08 20:37:32 +02:00
df7f1e819f
init sdram in PROM
2021-10-07 19:43:07 +02:00
455acac0c1
start working on some form of how-to, improve backplate for V1.2
2021-10-03 11:19:11 +02:00
0c8a06076e
start working on some form of how-to
2021-10-03 11:19:11 +02:00
1acb9a961e
commit untested cg3 emulation
2021-10-02 12:32:50 +02:00
07256fda8a
update backplate to V1.2
2021-10-02 07:53:10 +02:00
b228f00baa
update backplate to V1.2
2021-10-02 07:52:18 +02:00
f46337ac35
forgotten to commit extension for V1.0 with fan carrier
2021-10-01 13:30:14 +02:00
5982ff3ef0
bring back add_usb locally
2021-09-23 14:53:37 -04:00
918fe47747
minor stuff
2021-09-23 14:37:29 -04:00
ba734f0fa9
more ocnfigurability
2021-09-21 14:12:17 -04:00
4609e15dc6
missing xdr+
2021-09-20 13:55:00 -04:00
40e818c950
version-specific proms
2021-09-20 13:50:00 -04:00
6927ed4546
More V1.X stuff, still need to modularize the PROM. Also, why irqs other than 3 fails in Migen in V1.2 ???
2021-09-19 13:15:11 -04:00
fa2c511766
more V1.0 to V1.2 update stuff
2021-09-19 10:18:00 -04:00
34ed2b130a
apply patch from betrusted-io/gateware commit 817e284a3d92037b8cb0686735578d2bb60853e9
2021-09-07 05:11:28 -04:00
084d6ee3ca
More prep; splits CSR includes per-device
2021-09-06 12:21:54 -04:00
9e2a84d098
more V1.2
2021-09-06 09:43:16 -04:00
b40953b65c
Loops are easier to read...
2021-09-06 03:03:04 -04:00
e710b6b2ff
option to disable upper lane in AES/GCM isntructions; disable them in the code
2021-09-05 09:56:14 -04:00
13f7dc48d2
Put AES in the mul_clk domain
2021-09-05 04:42:42 -04:00
6954e719b7
fix errors
2021-09-05 04:41:33 -04:00
0b22dd98c3
4 AES inst -> just 1
2021-09-04 13:17:03 -04:00
984abbc656
USB configurability
2021-09-04 09:05:13 -04:00
e352323ae3
display all codes in engine_code
2021-09-04 09:04:58 -04:00
37bf0c5aa9
prelim for boot-time support
2021-09-04 09:04:40 -04:00
e820d105da
enough delay for longer-timed AES/GCM
2021-09-04 06:25:27 -04:00
e57cf9d9a8
preliminary work on AES256-GCM in the Engine
2021-09-04 05:52:11 -04:00
55298ec5b7
prelim work for V1.2
2021-09-04 02:10:26 -04:00
28ce3a7111
prelim work for V1.2
2021-09-04 02:07:37 -04:00
0ed24f16aa
USB ID pin left floating
2021-08-28 17:44:30 +02:00
12f239fbce
Update more stuff to V1.2
2021-08-28 17:05:07 +02:00
625b4185a8
Fewer LEDs, more interrupts, replace USB VBus power chip by something that might be available..., update signals file
2021-08-28 15:38:34 +02:00
110db38eb2
more AES/GCM
2021-08-26 10:27:55 -04:00
28b857851a
Full AES encrypt
2021-08-26 06:03:36 -04:00
d2218c6981
commit the experimental GCM/AES stuff in the engine
2021-08-25 09:44:28 -04:00
170c540cf7
ioctl on/off switch on stats + ctrl pgm
2021-08-23 04:48:05 -04:00
eede097217
CSRs don't support CDC... move Engine to sysclk ; also forgot to commit fsmstat
2021-08-22 10:27:28 -04:00
6d142636c2
Clean-up the master code (src)
2021-08-22 09:08:48 -04:00
8e94597b3a
Enable everything (using a Wishbone Crossbar instead of a Shared), some changes to Sbus timeouts, seems that everything play nice together now, also change Engine code to need fewer inputs
2021-08-22 03:54:00 -04:00
890033a0fe
move the last errored address to sbusfpga_stat ; add missing stat driver
2021-08-21 10:11:41 -04:00
2111020a0c
add an SBus statistics module (and discover a bug in the sbus lave timeouts and a lot of slave re-run)
2021-08-21 07:41:02 -04:00
67ad40c65e
(optional) checksumming in SDRAM DMA, change clocking on Engine, ...
2021-08-21 02:15:43 -04:00
d8914159b1
try to track down the issue...
2021-08-21 02:14:04 -04:00
15559b38b9
try to track down the issue...
2021-08-21 02:13:08 -04:00
ae7ba8115f
add ioctls for testing
2021-08-21 02:12:34 -04:00
bae310e0a3
more tests
2021-07-29 03:59:27 -04:00
42c5086885
Trying to integrate Bestrusted's Curve25519 engine ; trivial program works but not after a few repetition :-(
2021-07-25 06:52:05 -04:00
0c5e750453
Avoid some potential race conditions
2021-07-25 06:32:48 -04:00
6aa4734550
tune delays
2021-07-25 02:56:43 -04:00
acda04f456
SDRAM driver now complete enough to sunlabel/newfs
2021-07-24 11:53:05 -04:00
ef215942c0
bytes not blocks
2021-07-24 11:43:12 -04:00
b8e9211a77
driver update
2021-07-24 11:42:53 -04:00
aea1865b7b
commit the neorv32trgn-based trng
2021-07-20 07:45:51 -04:00
c258b75c57
typo
2021-07-18 13:06:50 -04:00
22e13886c0
update READMEs
2021-07-18 13:03:18 -04:00
9d88808b4f
SBus-OHCI driver
2021-07-18 13:02:43 -04:00
5094d1d213
re-enable USB in PROM, make sure the SDRAM request don't inadvertently kill the USB request
2021-07-18 12:44:48 -04:00
38e3431c7f
cleaning up some stuff, disable USB Host for testing SDRAM disk
2021-07-18 10:19:53 -04:00
023e84b734
swap on sbusfpga_sdram seems to work, but hogs the bus
2021-07-18 08:14:57 -04:00
c5e9a025b4
switch sdram access from Wishbone to dedicated port, seems to be more reliable
2021-07-18 05:08:37 -04:00
2f5b4eecfb
blk dev/dk support for sbusfpga_sdram
2021-07-18 02:52:37 -04:00
b86cf18e19
Oups forgot the DMA engine (this version with wishbone Converter)
2021-07-18 02:47:15 -04:00
0bd6b69dd9
Oups forgot the DMA engine (this version with wishbone Converter)
2021-07-18 02:47:06 -04:00
cd9fa81a82
access the SDRAM using a custom DMA; unreliable yet
2021-07-17 11:03:44 -04:00
4303270b53
minor renaming, think about buffering writes
2021-07-15 04:07:10 -04:00
6d4ba3aaa1
clean dmesg
2021-07-14 11:17:57 -04:00
Romain Dolbeau