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481260827c066f4e77bc3f4e156e01ec62da6449
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117 Commits

Author SHA1 Message Date
wfjm
481260827c ibdr_maxisys,sys_conf ready for buffered DL,PC,LP and dz11,ibtst 
- use type code instead of boolean for sys_conf_ibd_{dl11,lp11,pc11}
- add sys_conf_ibtst (enabled in all systems)
- add sys_conf_ibd_dz11 (enabled in all systems)
 2019-03-02 09:01:02 +01:00
wfjm
1206e5d938 add ibd_ibtst; tbench code for ibd_ibtst and sdreg 
- ibd_ibtst: added, an ibus tester device
- pdp11_sys70: instantiate ibd_ibtst (when sys_conf_ibtst = true)
- Rw11Cpu,RtclRw11Cpu: add ibmon setup and HasIbtst()
- tcl/ibd_ibtst/util.tcl: added, tcl support for ibd_ibtst
- tbench/w11a/test_w11a_sdreg.tcl: added, tbench for sdreg
- tools/tbench/w11a_ibtst/: added tbench for ibd_ibtst
 2019-03-01 09:05:29 +01:00
wfjm
8d323848b3 Some minor updates 
- top-level Makefile: drop w11a/arty_bram
- sys_w11a_s3: set BTOWIDTH 7 (was 6, must be > vmbox atowidth (6))
- RtclGet.ipp: use const& for oper() of string& and Rtime&
- *.Doxyfile: bump version to 0.77
- comment and docu updates
 2019-02-24 12:50:38 +01:00
wfjm
4a64a63c4c rbd_tester: use fifo_simple_dram 2019-02-23 09:37:19 +01:00
wfjm
0c395856d7 add memlib/fifo_simple_dram + test benches 
- add fifo_simple_dram: simple fifo with CE/WE interface, dram based
- add test benches for fifo_simple_dram, fifo_2c_dram, and fifo_2c_dram2
- add simclkv: test bench clock generator with variable period
 2019-02-22 19:09:42 +01:00
wfjm
913fe9b399 update message filters 
- vmfset: now tested for viv 2017.2 and 2018.3
- imfset: now tested for ISE 14.7
 2019-02-15 18:44:55 +01:00
wfjm
80fbad98c6 add resource lines for viv 2017.2 and 2018.3 2019-02-10 09:04:52 +01:00
wfjm
39a6280cda remove iist from Spartan-3,6 designs 2019-02-09 09:13:46 +01:00
wfjm
c47ac81e78 down rate sys_w11a_arty to 75 Mhz for viv 2018.3 2019-02-08 20:30:19 +01:00
wfjm
51c2cf328c add forgotten file for Arty S7 with MIG 2019-02-08 19:48:57 +01:00
wfjm
f613babe57 add w11a system for Arty S7 with MIG 2019-02-03 09:23:05 +01:00
wfjm
3cb0bc6924 add MIG support for Arty S7 2019-02-02 09:36:23 +01:00
wfjm
302dc20cb7 add w11a system for Nexys4 DDR with MIG 2019-01-27 09:54:19 +01:00
wfjm
b238f9bce2 add sys_tst_sram_n4d (memory tester for Nexys4 DDR) 2019-01-26 20:43:16 +01:00
wfjm
69e3fb5e68 add sys_tst_mig_n4d (MIG tester for Nexys4 DDR) 2019-01-18 19:34:15 +01:00
wfjm
74ad445c1e Some minor updates: 
- tbrun: add --list option
- ti_w11: add add -ar,-n4d (ddr versions)
- travis: run all  sys_tst_sram,sys_w11a also for arty (cover ddr)
- tst_mig/test_mem.tcl: add low level iface tests
- comment changes
 2019-01-13 09:46:54 +01:00
wfjm
3a8da10b96 add MIG support for Nexys4 DDR 2019-01-12 09:48:18 +01:00
wfjm
dd7cdfeceb add w11a system for Arty with MIG 2019-01-04 09:19:00 +01:00
wfjm
cb7b906089 Add memory tester for Arty and MIG 
- sys_tst_sram_arty: add system and tb
- sramif_mig_arty: add SRAM to DDR via MIG adapter for arty
- cdc_pulse: add clock domain crossing for a slowly changing value
- cdc_vector_s0: add ENA port (now used in cdc_pulse)
- tst_mig/util.tcl: test_rwait: add optional lena argument
- viv_tools_build.tcl: downgrade SSN critical warnings to warnings
 2019-01-03 09:15:07 +01:00
wfjm
0e87dd8670 add sramif2migui: w11a SRAM to MIG UI interface core 2019-01-02 10:06:25 +01:00
wfjm
f50a85e646 add sys_tst_mig_arty system: a MIG tester 2019-01-01 22:41:44 +01:00
wfjm
14362b2a56 Add basic DDR memory support 
- arty board support
- viv_tools_build: export log and rpt generated in OOC synthesis runs
- s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper
- s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk
- cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input
- migui_core_gsim: highly simplified MIG UI simulation model
 2018-12-31 10:00:14 +01:00
wfjm
cf6c0ed8e0 cleanup not longer used directory 2018-12-30 10:59:24 +01:00
wfjm
b8dfa6d41e get ready for w11a_V0.753 release 
- rtl/sys_gen/*/*.vhd: drop superfluous genlib call
- rtl/sys_gen/*/*.vmfset: accomodate recent code changes
- tools/bin/tbrun: show correct 'found count' in summary message
- tools/dox/*.Doxyfile: push version to 0.753
- tools/src/librtools/Rtime.ipp: change list-init make some gcc happy
 2018-12-29 14:14:08 +01:00
wfjm
89732fe3e0 update xviv_msg_filter 
- add c type rules for 'count-only' filters
- add support for bitstream generation checking ([bit] section)
- update vmfsets
 2018-12-26 09:40:03 +01:00
wfjm
674762d6d8 consolidate clock generation in 7-Series designs 
- s7_cmt_1ce1ce: add clock generator block used in many 7-Series designs
- sys_gen/*/*: use s7_cmt_1ce1ce in 7-Series designs
- tbcore_rlink: wait 40 cycles after CONF_DONE
- serport_master_tb: add 100 ps RXSD,TXSD delay to allow clock jitter
 2018-12-21 09:06:16 +01:00
wfjm
233730885d comment&code cosmetics; minor changes 2018-12-08 09:25:25 +01:00
wfjm
5d34d1fad6 ensure that essential vivado warnings are not discarded 
- xviv_msg_filter: display INFO Common 17-14 'further message disabled'
- viv_tools_build.tcl: increase message limits (all 200, some 5000)
- sys_w11a_*.vmfset: correct for thus far missed entries
 2018-12-07 19:38:32 +01:00
wfjm
a3bf3519d9 remove ISE build support for 7Series designs 2018-12-01 13:07:59 +01:00
wfjm
e1abc27983 comment&code cosmetics; minor changes 2018-11-11 09:50:46 +01:00
wfjm
22bb8e011c reorganize dcm/mmcm/ppl sim models 
- sfs_gsim_core: new common simulation core
- {dcm,s6_cmt,s7_cmt}_sfs_gsim: use now sfs_gsim_core
- s7_cmt_sfs_tb: removed, use now sfs_gsim_core
- rtl/bplib/*/tb/tb_*: use now sfs_gsim_core
- tst_serloop/nexys*/tb/tb_tst_serloop*_n*: use now sfs_gsim_core
 2018-11-09 17:48:56 +01:00
wfjm
0913863793 comment&code cosmetics; minor changes 2018-11-03 10:30:00 +01:00
wfjm
90db21ac5e update vivado design vmfset files 2018-10-14 15:06:24 +02:00
wfjm
37b2d63281 finalize IDEC and PERFEXT wiring 
- ibdr_maxisys: add IDEC port, connect to EXTEVT of KW11P
- sys_w11a_*.vhd: use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
- kw11p and dmpcnt now fully setup
 2018-10-14 15:02:45 +02:00
wfjm
3eedd7f5c8 comment&code cosmetics; minor changes 2018-10-14 14:57:39 +02:00
wfjm
c7e606d9b0 use DM_STAT_EXP for signals exported by pdp11_sys70 
- pdp11_sys70: drop ITIMER,DM_STAT_DP, use DM_STAT_EXP, add PERFEXT port
- pdp11_sequencer: drop ITIMER port, use DM_STAT_SE.itimer
- sys_w11a_*.vhd: use DM_STAT_EXP
- some re-wiring, no functional change to CPU or IO system
 2018-10-13 15:18:59 +02:00
wfjm
f40108cb95 drop DM_STAT_SY, add DM_STAT_CA and cache monitoring 2018-10-07 08:50:11 +02:00
wfjm
1be14ad15f Integrate dmpcnt in all w11 designs and backend 
- pdp11_sequencer: add DM_STAT_SE.(cpbusy,idec)
- pdp11_sys70: only preliminary set of signals, cache signals kludged
 2018-09-30 09:35:30 +02:00
wfjm
f838fc3b4d add pdp11_dmpcnt: performance counters 2018-09-29 17:33:33 +02:00
wfjm
4df1d3e549 minor comment corrections/additions 2018-09-21 19:35:31 +02:00
wfjm
ff7b4fad97 integrate KW11-P in all w11 designs 2018-09-15 17:27:46 +02:00
wfjm
17ede0047a add ibd_kw11p: KW11-P prog clock 2018-09-15 15:23:47 +02:00
wfjm
40d48680e9 finalize w11a_V0.752 release 2018-08-26 13:54:48 +02:00
wfjm
088f57df2c prepare w11a_V0.752 release 2018-08-26 10:03:24 +02:00
wfjm
010c79c0fc add w11a port to Arty S7 (BRAM only, sim-tested only) 2018-08-25 07:59:59 +02:00
wfjm
b24fd9a3cb add Digilent Arty S7 board support 2018-08-25 07:58:05 +02:00
wfjm
ac16d6d27e *.vmfset: update rules to cover 2017.4-2018.2 2018-08-24 20:52:21 +02:00
wfjm
b6074a354f _ssim.vbom: fix incorrect aif target 2018-08-12 08:41:52 +02:00
wfjm
286a8cdaff add forgotten tb_c7_sram_memctl 2018-08-10 22:17:22 +02:00
wfjm
5493c0f4f2 minor docu updates, add INSTALL_quickstart 2018-08-04 15:07:12 +02:00